This invention is in the field of direct digital signal synthesizers generating periodic signals at microwave frequencies.
Direct digital synthesizers (DDS) use a plurality of digital data processing blocks to generate a frequency and phase tunable output referenced to a fixed frequency clock source. Generally, the fixed frequency clock source is divided down within the DDS architecture by a scaling factor specified using a digital tuning word. This digital tuning word is typically 24 to 48 bits long, allowing a wide degree of tuning resolution with respect to the fixed frequency clock source.
Another aspect of DDS operation is that in addition to the output frequency, the phase of the output can also be specified using a digital input. Thus, the parameters of the output from a DDS is not only frequency, but also phase, referenced to the clock source.
Typical DDS structures can generate an output signal specified in terms of both frequency and phase upon digital command for applications such as local oscillators quadrature (I/Q) synthesizers, GMSK and ramped FSK, and the like.
It is desirable to make frequency/phase changes quickly, even within one cycle of the waveform. In general, the constraints precluding high output frequency or rapid phase change come from various device limitations. One example of a device limitation is that the clock source frequency required for fast, sub-cycle change may be too high for devices created using existing semiconductor processes. Currently, high speed operation requires that the digital circuitry generating the output waveform switch at full clock speed frequencies. Such high speed operation uses substantial amounts of power, as well as imposing the need for high quality transistors having high frequency operating capability (high unity current gain transition frequency, fT). High power consumption, coupled to high cost process for high ft, structures, burdens state of the art systems with disadvantageous economic constraints.
Some configurations require the use of high speed random access memories to store digital bits required for conversion. Reducing the speed of these memories is an objective of the invention.
A direct digital synthesizer (DDS) is described for generating an analog output. The analog output is a sinusoidal waveform having a a variable frequency within a time duration.
The DDS comprises:
a memory (402, 404, 406, 335) for storing pre-computed digital values defining said sinusoidal waveform;
a barrel shifter (311, 408, 410, 412) for reading contents of said memory (402, 404, 406, 335) for presenting said digital values from said memory to an input of a multiplexer (321, 323, 325, 327, 416, 418, 420) at a first rate determined by a a first clock (434, 333).
The multiplexer (416, 418, 420) has an output connected to a Digital to Analog converter (329, 432). The Digital to Analog converter converts the digital values presented by the multiplexer (416, 418, 420) to the analog output at a second rate determined by a second clock (331).
The barrel shifter shifts the digital values using a plurality of pipelines and n-bit wrap-around registers (436).
The pre-computed digital values defining said sinusoidal waveform are pre-computed and stored within a storage means (memory) during said duration. Some of said pre-computed digital values are pre-computed using a numerically controlled oscillator (315). Others of said pre-computed digital values are pre-computed using a simulation of a xcex94xcexa3 modulator (337).
Pre-computed digital values are routed from a storage means (335) using a bus exchange switch (309) to the barrel shifter (311). Other values are computed within NCO 315, routed through Bus exchange switch 309 to either a storage location (RAM 335) or barrel shifter 311.